1. Technical Field
The present invention relates to a process for manufacturing a multi-drain power electronic device integrated on a semiconductor substrate.
More specifically, the invention relates to a process for manufacturing a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed.
The invention particularly, but not exclusively, relates to a process for manufacturing a multi-drain power MOS transistor and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, power MOS devices with a breakdown voltage BV comprised between 200 and 1000V have a high output resistance (Ron) mainly due to the epitaxial drain layer resistance which is used to withstand high voltages, and it depends on the dopant concentration of the epitaxial layer itself.
However, the possibility is also known of obtaining power MOS devices with a low output resistance and a high breakdown voltage BV by modifying the epitaxial layer concentration.
A known MOS device meeting this need is shown in FIG. 1, globally indicated with 3. Such a MOS power device 3 is of the so called multi-drain type and it comprises a heavily doped semiconductor substrate 1, in particular of the N+ type, whereon a semiconductor epitaxial layer 2 of the same type of N is formed.
The epitaxial layer 2 forms a drain layer common by a plurality of elementary units forming the MOS power device 3. Each elementary unit comprises a body region 4, in particular of the P type, formed on the epitaxial layer 2.
In the epitaxial layer 2, below each body region 4, there is a column region 5, in particular of the P type, which extends downwards for substantially the whole thickness of the epitaxial layer 2 towards the semiconductor substrate 1.
In particular, each column region 5 is aligned and in contact with a respective body region 4 of an elementary unit of the MOS power device 3.
In such way, as shown in FIG. 2, wherein the concentration of the epitaxial layer is shown as a function of its thickness, the N epitaxial layer 2 of the MOS power device 3 thus formed has a constant resistivity. Also the column regions 5 have a constant concentration along their whole column extension, as shown in FIG. 3, wherein the concentration of the column regions 5 is shown as a function of their thickness.
The MOS power device 3 also exhibits, inside the body regions 4, heavily doped source regions 6, in particular of the N type.
The surface of the epitaxial layer 2 is thus covered with a thin gate oxide layer 7 and with a polysilicon layer. Openings are provided in the polysilicon layer 8 and in the thin gate oxide layer 7 to uncover portions of the epitaxial layer 2 surface in correspondence with each source region 6. An insulating layer 9 completely covers the polysilicon layer 8 and it partially covers the source regions 6, so as to enable a source metallic layer 10 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is also provided on the lower surface of the semiconductor substrate 1.
It is to be noted that the presence of the column regions 5 thus allows to reduce the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage BV of the MOS power device 3 as a whole. With this type of devices it is thus possible to reach a predetermined breakdown voltage BV with a resistivity of the epitaxial layer 2 being lower than that used in conventional MOS devices and, in consequence, to obtain power MOS transistors with reduced output resistance.
Moreover, as shown in FIG. 4, MOS power devices formed by means of a plurality of elementary units comprising column regions 5 exhibit an output resistance, shown by curve A, being breakdown voltage BV equal, lower not only than the one, shown by curve B, of conventional MOS devices but also lower than the so called ideal limit of silicon, shown by curve C.
To better understand the dynamics of these known devices, with reference to FIGS. 6 to 10, a method is now described for forming the multi-drain MOS power device 3 of FIG. 1.
In particular, on the heavily doped semiconductor substrate 1 of the N+ type an epitaxial layer 2 is formed comprising, on the bottom, a first epitaxial layer 2a of the N type with a dopant concentration corresponding to a resistivity ρ.
After having formed a first photolithographic mask on the first epitaxial layer 2a, a trench in this first epitaxial layer 2a through the first photolithographic mask for forming a zero level indicator not shown in the figures.
A second mask is thus formed on such first epitaxial layer 2a wherein a plurality of openings are formed.
Through these openings a first implant step of P dopant is carried out for forming first implanted regions 5a, as shown in FIG. 6.
As shown in FIG. 7, on the first epitaxial layer 2a a second N epitaxial layer 2b is formed with a dopant concentration corresponding to the resistivity ρ.
A third mask is then formed, aligned with the second mask by means of the zero level indicator, on the second epitaxial layer 2b wherein a plurality of openings are formed.
Through these openings a second P dopant implant step is carried out in the second epitaxial layer 2b for forming second implanted regions 5b. 
As shown in FIG. 8, on the second epitaxial layer 2b, a third epitaxial layer 2c of the N type is then formed having a dopant concentration corresponding to the resistivity ρ.
A fourth mask is then formed, aligned with the second and the third mask by means of the zero level indicator on the third epitaxial layer 2c wherein a plurality of openings are formed.
Through these openings a third P dopant implant step is carried out in the third epitaxial layer 2c for forming, by means of a subsequent thermal diffusion process, third implanted regions 5c. 
As shown in FIG. 9, on the third epitaxial layer 2c, the fourth N epitaxial layer 2d is then formed having a dopant concentration always corresponding to the resistivity ρ.
A fifth mask is then formed, aligned with the second, third and fourth mask by means of the zero level indicator on the fourth epitaxial layer 2d wherein a plurality of openings are formed.
Through these openings a fourth P dopant implant step is carried out in the fourth epitaxial layer 2d for forming fourth implanted regions 5d. 
Obviously, it is possible to provide any number of masking steps and subsequent dopant implantation for forming a plurality of implanted regions aligned and arranged in a succession of epitaxial layers overlapped onto each other.
As shown in FIG. 10, as last on the fourth epitaxial layer 2d, a fifth N epitaxial layer 2e is then formed having a fifth dopant concentration always corresponding with the resistivity ρ.
A sixth mask is then formed, aligned with the second, third, fourth and fifth mask by means of the zero level indicator on the fifth epitaxial layer 2e wherein a plurality of openings are formed.
Through these openings a fifth P dopant implant step is carried out in the fifth epitaxial layer 2e for forming the body regions 4 of the MOS power device 3, as previously shown with reference to FIG. 1.
A seventh mask is then formed, aligned with the second, third, fourth, fifth and sixth mask by means of the zero level indicator on the fifth epitaxial layer 2e wherein a plurality of openings are formed.
Through these openings a sixth N+ dopant implant step is carried out in the fifth epitaxial layer 2e for forming the source regions 6 of the MOS power device 3.
A thermal process of thermal diffusion is then carried out for diffusing the implanted regions 5a, 5b, 5c, 5d, the body regions 4 and the source regions 6 of the MOS power device 3 and so that the implanted regions 5a, 5b, 5c, 5d form a single column region 5 aligned and in contact with the body region 4.
In particular, as shown in FIG. 1, after the diffusion process of the implanted regions 5a, 5b, 5c, 5d, each column region 5 shows itself as a column structure comprising “spherical bubbles” of the P type.
The process is then completed with the conventional manufacturing steps including the formation of the thin gate oxide layer 7 and the polysilicon layer 8 on the surface of the epitaxial layer 2. Openings are then provided in the polysilicon layer 8 and in the thin gate oxide layer 7 until they uncover portions of the surface of the epitaxial layer 2 aligned with each source region 6. The insulating layer 9 is formed until it completely covers the polysilicon layer 8 and it partially covers the source regions 6, so as to allow a source metallic layer 10 formed on the MOS power device 3 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is finally formed on the lower substrate of the semiconductor substrate 1.
It is to be noted that the presence of the column regions 5 hooked to the body regions 4 empties the drain region 2, enabling the MOS power device 3 thus formed to withstand a predetermined voltage applied from the outside to the device even when there are dopant high concentrations in the epitaxial layer 2 (which is a conductive layer of the N type, in the case of devices with channel N like the one shown with reference to FIGS. 1 and 6-10).
Moreover, the breakdown voltage BV, that the MOS power device 3 thus obtained can withstand, varies, the resistivity in the epitaxial layer 2 being equal, with the dopant concentration in the column regions 5 (which are, in the example shown in FIGS. 1 and 6-10, of the P type).
In particular, as shown in FIG. 4a, the breakdown voltage BV varies when the P dopant concentration in the drain epitaxial layer 2 increases: in particular, the breakdown voltage is maximum when the N dopant concentration in the drain epitaxial layer 2 is completely balanced by the P dopant concentration introduced by a P implant dose ΦE used to form the column regions 5. This condition is indicated as “charge balance”.
If during the first P dopant implant step for forming first implanted regions 5a an implant dose Φ is used being lower than the implant dose ΦE, the final concentration of the column regions 5 is lower than the concentration of the column regions 5 obtained by means of the implant dose ΦE used in the case of “charge balance”. This condition is indicated as “ρ charge fault” or, equivalently, “n charge excess”. If during the first P dopant implant step for forming first implanted regions 5a an implant dose Φ is used being higher than the implant dose ΦE, the concentration of the column regions 5 is higher than the concentration of the column regions 5a obtained in the case of “charge balance”. This condition is indicated as “ρ charge excess” or, equivalently, “n charge fault”.
As it has been said, under both the described charge excess/fault conditions, the breakdown voltage BV of the devices obtained is lower than the one obtained by using the implant dose ΦE.
Then, for realizing the charge balance conditions balancing the charge N obtained epitaxially with the implanted charge P is necessary.
However, the layers formed by epitaxy exhibit values of a predetermined design quantity, such as for example the thickness or the resistivity of the layer, which vary from layer to layer and inside the same layer. Moreover, such values are different from those of the layers formed by means of implantation.
Since in the devices of the Multi Drain type to obtain the highest breakdown voltage BV it is necessary to balance and control the charge introduced by epitaxy, for example of the N type and the one introduced by implantation for example of the P type, the different values of the predetermined design quantities inside the single layers formed by epitaxy or by implantation are statistically a cause of the device failure, i.e., the predetermined design breakdown voltage BV is not reached and thus the productive yield of the final device is decreased.
Moreover, in multi-drain devices, the resistivity of the epitaxial layer 2 fixes the distance between two adjacent column regions 5 and thus the pitch of the entire MOS power device 3 thus formed.
In particular, by decreasing the resistivity of the epitaxial layer 2 and thus increasing the concentration of this layer it is necessary to form devices 3 with reduced (lateral) dimensions, so as to ensure a good resistance of the electric field in operation. To obtain these conditions it is thus necessary to reduce the thickness of the drain layer. However, by using reduced thickness for the drain epitaxial layer 2 to obtain MOS power devices which can withstand a predetermined voltage equal to the one which can be obtained with devices formed with greater thermal budgets and pitches, it is necessary to increase the number of the epitaxial layers forming the drain epitaxial layer and relative implant steps forming the P column regions 5.
This solution remarkably increases the manufacturing costs of the MOS power devices 3 thus formed.
In fact, the breakdown voltage BV the device 3 must be able to withstand defines the height of the column regions 5: for a device of 500 V it is comprised between 20 and 30 μm.